1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to semiconductor devices encompassing buried oxide structures.
2. Description of the Related Art
700V class lateral power MOSFETs are often built into intelligent power devices as output elements, for example. Horizontal or lateral DMOSFETs generally have less input capacitance and feedback capacitance than vertical DMOSFETS, and thus are beneficial in high-speed operations. However, with a lateral DMOSFET compared with a vertical MOSFET of the same drain breakdown voltage level, ON resistance is equal or greater, and switching power loss increases. Because of this, in order to expand applications to high power switching power supplies that further reduce electrical power consumption or increase output current, it is essential to reduce the ON resistance without reducing the drain breakdown voltage of a power MOSFET.
Up until presently, SC (Single conduction) structures, DC (double conduction) structures, and TC (triple conduction) structures have been proposed for use as a lateral MOSFET Structure put forth above.
A 700 V class lateral MOSFET, having a DC structure produced with the objective of reducing ON resistance, is already being implemented at present. Using an ion implantation apparatus with high acceleration energy, the DC structure having a dual pass conduction channel is formed within an n type drift region, realizing low ON resistance.
Also a lateral MOSFET, that has a triple pass conduction channel formed within an n type drift region, and having a TC structure exhibiting even less ON resistance than a DC structure, is being implemented with equal or greater breakdown voltage (See, “Improvements in drain breakdown voltage of 700V lateral MOSFETS according to TC (Triple Conduction) structure” Author: Mr. Yasuhiro Takehana et. al., DENKI GAKKAI DENSHI DEBAISU/HANDOUTAI DENRYOKU HENKAN GOUDOU KENKYUKAI, EDD-03-48, SPC-03-115, 2003/09, P. 21–26).
Earlier Silicon On Insulator (SOI) structure lateral MOSFETs include, as shown in FIG. 1, a support substrate 2 made from semiconductor substrate, a buried oxide film (BOX film) 3, an active layer (n− layer) 4, a base region 5, a back gate region 6, a source region 7, a drain region 8, a source electrode 9, a drain electrode 10, a gate electrode 11, and a gate insulator film 12.
In a MOSFET implementing SOI, because the size of the depletion layer is governed by the thickness of the active layer and the thickness of the buried oxide film, it is essential to provide a thick active layer 4 in order to achieve a high breakdown voltage. If the active layer 4 is thick, formation of the element isolation region and wafer processing itself become difficult. And in a case in which a super junction, which enables high breakdown voltage and low ON resistance, is formed in a SOI wafer, if the electric potential of the substrate is established as ground or floating, it is impossible to make use of a high breakdown voltage enabled by the super junction while concentrating an electric field at the drain electrode or source electrode. Further, compared to a vertical MOSFET that flows a current vertically, because it is difficult to increase a pn junction, effectiveness of reduction of ON resistance (Ron) tends to decrease.